In general, a delay locked loop (“DLL”) is a circuit that compares phases of the rising edges of signals from an input reference clock and an output clock through a phase detector (“PD”). FIG. 1 illustrates an embodiment of a conventional locked loop circuit for the general purpose described above. On the basis of the result of the comparison of the rising edges of the input reference clock and the output clock through a PD, a DLL implements control using a charge pump (“CP”) and a capacitor (C), configured as shown. The delay time of the delay line includes several delay cells to match the rising edges of the input reference and output clocks.
When a DLL is used in a system that requires an accurate delay time, it is important that the delay time of the delay line be the same as a period T. If the actual initial delay time between the output clock and the input reference clock is less than 0.5T or larger than 1.5T, the DLL does not operate properly. The DLL's may fail to operate properly because the delay time of the delay line tends to be locked at 0 or nT (where n=2, 3, . . . ), respectively, due to the operational characteristics of a general phase detector (“PD”). A problem with conventional phase detectors is that because the delay time of delay cells used in an analog delay line may vary greatly depending on the control voltage, the delay time may be less than 0.5T or larger than 1.5T, resulting in inaccurate delay times.
FIG. 2 is another conventional implementation of a DLL showing a phase detector. A delay line (41) is composed of a number of unit delayers (d1-dn) and a phase detector (43). FIG. 3 is a further diagram of the phase detector shown in FIG. 2, which is composed of three flip-flops (61, 63, 65) and an end gate (67).
The phase detector (43) receives electrical impulses from the input reference clock (CLKIN) and the output clock (CLKOUT) of the delay line (41—FIG. 2) and a middle clock (CLKMID). The electrical signal can be selected from the two clocks (CLKIN, CLOUT) for comparison and the DLL will apply a control signal (VCON) to the delay line (41) through a charge pump circuit (45) on the basis of the result of such comparison, so that the delay line (41) may not be locked to a delay time of 2T. Conventional DLLs can prevent the delay line from being locked to a delay time of 2T, but cannot prevent locking to a higher delay time of nT (where n=3, 4, . . . ).
Another conventional DLL is shown in the block diagram of FIG. 4, including a replica delay line (41). A further illustration of the replica delay line (41) is shown in FIG. 5, which includes a clock (Ref-CLK). The clock and corresponding waveforms are illustrated in the diagram of FIG. 6. As illustrated in FIG. 6, a general DLL (40) is added with a replica delay line (41), wherein the replica delay line (41) tunes and sets the delay line within a correct lock range, while the DLL (40) provides for accurate control of delay time. Also, conventional operational methods for the replica delay line (41) shown in FIGS. 5 and 6 rely upon the probability that the replica delay line (41), using one delay cell and the delay time of one delay cell, being less than 1.5T is greater than the delay time of the entire delay line being less than 1.5T. However, conventional methods also have a drawback, requiring an additional DLL when the delay time of one delay cell is greater than 1.5T.
FIG. 7 is the diagram of yet another exemplary embodiment of a conventional DLL. As illustrated, a method uses the output (Φ1-Φ9) of each delay cell of the delay line (71) to determine whether the rising edge of the DLL output clock is within the correct lock range of a lock detector (72). The lock detector (72) latches the rising edge of the output of each delay cell to the input reference clock and determines a false lock using a combinational circuit. If the lock detector (72) determines a false lock, the phase detector (73) outputs an “up” or a “down” signal in accordance with the determination of the lock detector (72) regardless of the resulting value from a comparison of the phases between the rising edges of the input reference clock (ckref) and the output clock.
However, while conventional DLLs can avoid a false lock up to (m−1)T, when the delay line is composed of m delay cells, the delay line remains restricted to a delay time of nT (n=m, m+1, . . . ). Thus, there is a need for a DLL which is not restricted to a delay time of nT and which avoids the inaccurate delay times of conventional DLLs.